The-OpenROAD-Project / OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
The-OpenROAD-Project / OpenROAD
logisim-evolution / logisim-evolution
Digital logic design tool and simulator
verilator / verilator
Verilator open-source SystemVerilog simulator and lint system
steveicarus / iverilog
Icarus Verilog
The-OpenROAD-Project / OpenROAD-flow-scripts
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
open-sdr / openwifi
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
SpinalHDL / VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation
openhwfoundation / cva6
The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.
alexforencich / verilog-ethernet
Verilog Ethernet components for FPGA implementation
cocotb / cocotb
cocotb: Python-based chip (RTL) verification
SpinalHDL / SpinalHDL
Scala based HDL
riscv-mcu / e203_hbirdv2
The Ultra-Low Power RISC-V Core
pulp-platform / axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
clash-lang / clash-compiler
Haskell to VHDL/Verilog/SystemVerilog compiler
verilog-to-routing / vtr-verilog-to-routing
Verilog to Routing -- Open Source CAD Flow for FPGA Research
gtkwave / gtkwave
GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing.
vicharak-in / shrike
Low cost microcontroller + FPGA board for makers , hobbyist and student for endless possibility.
adam-maj / tiny-gpu
A minimal GPU design in Verilog to learn how GPUs work from the ground up
chipsalliance / chisel
Chisel: A Modern Hardware Design Language
darklife / darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
stnolting / neorv32
🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
analogdevicesinc / hdl
HDL libraries and projects
chipsalliance / verible
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
google / xls
XLS: Accelerated HW Synthesis
FPGAwars / icestudio
:snowflake: Visual editor for open FPGA boards
olofk / fusesoc
Package manager and build abstraction tool for FPGA/ASIC development
chili-chips-ba / wireguard-fpga
Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door is wide open for backdoor scrutiny, be it related to RTL, embedded, build, bitstream or any other aspect of design and delivery package. Bujrum!
siliconcompiler / siliconcompiler
Modular hardware build system
MikePopoloski / slang
SystemVerilog compiler and language services
veryl-lang / veryl
Veryl: A Modern Hardware Description Language
FPGAwars / apio
:seedling: Open source ecosystem for open FPGA boards
open-sdr / openwifi-hw
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware
nickg / nvc
VHDL compiler and simulator
VUnit / vunit
VUnit is a unit testing framework for VHDL/SystemVerilog
TerosTechnology / vscode-terosHDL
VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
openhwfoundation / core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
bespoke-silicon-group / basejump_stl
BaseJump STL: A Standard Template Library for SystemVerilog
8bitworkshop / 8bitworkshop
web-based IDE for 8-bit programming and Verilog development
dalance / svls
SystemVerilog language server
StefanSchippers / xschem
A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
Tencent / wave-mcp
Open-source, license-free MCP server for RTL waveform debug: reads FST waveforms (VCD/FSDB auto-convert) plus a SystemVerilog netlist, with 34 tools covering driver analysis, value/X tracing, pass-fail waveform diff, a browser wave viewer the agent drives, and pre-simulation static analysis.
penberg / titania
Project Titania is a complete large language model system, from transformer to transistor, simple enough for one person to understand.
exeex / edge-cores
The shortest path from PyTorch to custom ASICs.
a2307588073-arch / zynq-yolov3-tiny-accelerator
INT8 single-class YOLOv3-Tiny accelerator and OV5640-to-HDMI bare-metal demo for Xilinx Zynq-7000 XC7Z100, with PyTorch training and parameter-export tools. Topics yolov3-tiny, fpga, zynq-7000, xc7z100, verilog, vivado, vitis, pytorch, int8-quantization, object-detection, axi4-stream, ov5640, hdmi, embedded-systems, computer-vision
TinyTapeout / ttsky-verilog-template
Submission template for Tiny Tapeout SKY130 (ChipFoundry) shuttles - Verilog HDL Projects
YutongChenVictor / NPU-E2E
End-to-End NPU: RTL systolic array → AXI4 SoC → TVM compiler → FPGA inference
liujianyu20021122 / RTL-ASS
Codex-first, vendor-neutral RTL coding and verification skill using open-source tools
SweiryDev / MicroCNN-TangNano20k
SystemVerilog SoC implementing MicroCNN accelerator on the Tang Nano 20K for BloodMNIST image classification.
haruto89610 / rtl-nic
Source-available SystemVerilog RTL for a custom FPGA Ethernet datapath with ARP, IPv4, UDP, and specialized TCP transport control.
IvesLiu1026 / NYCU-ICLAB-2026-Fall
Selected digital IC designs, architecture explanations, and measured results for NYCU ICLAB, Fall 2026.
qingxuanxx / sv_uvm_axi_notes
数字IC验证学习笔记：SV/UVM/AMBA总线（AXI/APB/AHB/AXI-Lite/AXI-Stream）+ 数字IC验证校招面经
cwu766485-ctrl / LumenRV32
A lightweight RV32I RISC-V processor core implemented in Verilog for architecture and RTL design practice.
adibis / brokenBench
Systemverilog and UVM exercises inspired by ziglings
nand2mario / zSST
Voodoo-1 3D graphics chipset in SystemVerilog
nand2mario / z486
80486-class CPU with integrated floating-point in SystemVerilog
rugbedbugg / RookShift
Chess960-based steganography that converts arbitrary byte strings into a sequence of Chess960 starting positions