openhwfoundation / cva6

# CVA6 RISC-V CPU 
CVA6 is a 6-stage, single-issue, in-order CPU which implements the 64-bit RISC-V instruction set. It fully implements I, M, A and C extensions as specified in Volume I: User-Level ISA V 2.3 as well as the draft privilege extension 1.10. It implements three privilege levels M, S, U to fully support a Unix-like operating system. Furthermore, it is compliant to the draft external debug spec 0.13.
It has a configurable size, separate TLBs, a hardware PTW and branch-prediction (branch target buffer and branch history table). The primary design goal was on reducing critical path length.
The CVA6 core is part of a vivid ecosystem. In this document, we gather pointers to this ecosystem (building blocks, designs, partners...).
A performance model of CVA6 is available in the `perf-model/` folder of this repository.
It can be used to investigate performance-related micro-architecture changes.
# Quick setup
The following instructions will allow you to compile and run a Verilator model of the CVA6 APU (which instantiates the CVA6 core) within the CVA6 APU testbench (corev_apu/tb).
Throughout all build and simulations scripts executions, you can use the environment variable `NUM_JOBS` to set the number of concurrent jobs launched by `make`:
- if left undefined, `NUM_JOBS` will default to 1, resulting in a sequential execution
of `make` jobs;
- when setting `NUM_JOBS` to an explicit value, it is recommended not to exceed 2/3 of
the total number of virtual cores available on your system. 
1. Checkout the repository and initialize all submodules.
 [code] 
2. Install the GCC Toolchain build prerequisites then the toolchain itself.
:warning: It is **strongly recommended** to use the toolchain built with the provided scripts.
3. Install `cmake`, version 3.14 or higher.
4. Set the RISCV environment variable.
 [code] 
5. Install `help2man` and `device-tree-compiler` packages.
For Debian-based Linux distributions, run :
 [code] 
6. Install the riscv-dv requirements:
 [code] 
7. Run these commands to install a custom Spike and Verilator (i.e. these versions must be used to simulate the CVA6) and these tests suites.
 [code] 
# Tutorials
* **Running Simulations**
* **ASIC Implementation**
* **FPGA Implementation and running an OS**
* **Instruction Tracing**
# Directory Structure
The directory structure separates the CVA6 RISC-V CPU core from the CORE-V-APU FPGA Emulation Platform.
Files, directories and submodules under `cva6` are for the core _only_ and should not have any dependencies on the APU.
Files, directories and submodules under `corev_apu` are for the FPGA Emulation platform.
The CVA6 core can be compiled stand-alone, and obviously the APU is dependent on the core.
The top-level directories of this repo:
* **ci**: Scriptware for CI.
* **common**: Source code used by both the CVA6 Core and the COREV APU. Subdirectories from here are `local` for common files that are hosted in this repo and `submodules` that are hosted in other repos.
* **core**