The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.
The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
64-bit RISC-V (RV64GC) core that boots Linux on an Arty A7 FPGA. Designed entirely by Claude Code: the specifications, RTL, verification and documents were all written by the AI.
Sigil: an in-house RV64GCV RISC-V core and SoC with hardware hashing (SHA-2/SHA-3/Keccak) and signature verification (Ed25519, secp256k1)