The-OpenROAD-Project / OpenROAD

# OpenROAD
## About OpenROAD
OpenROAD is the leading open-source, foundational application for
semiconductor digital design. The OpenROAD flow delivers an
Autonomous, No-Human-In-Loop (NHIL) flow, 24 hour turnaround from
RTL-GDSII for rapid design exploration and physical design implementation.
 [code] 
## OpenROAD Mission
OpenROAD eliminates the barriers
of cost, schedule risk and uncertainty in hardware design to promote
open access to rapid, low-cost IC design software and expertise and
system innovation. The OpenROAD application enables flexible flow
control through an API with bindings in Tcl and Python.
OpenROAD is used in research and commercial applications such as,
- OpenROAD-flow-scripts
 from OpenROAD
- OpenLane from
 Efabless
- Silicon Compiler
 from Zero ASIC
- Hammer
 from UC Berkeley
- OpenFASoC from
 IDEA-FASoC for mixed-signal design flows
OpenROAD fosters a vibrant ecosystem of users through active
collaboration and partnership through software development and key
alliances. Our growing user community includes hardware designers,
software engineers, industry collaborators, VLSI enthusiasts,
students and researchers.
OpenROAD strongly advocates and enables IC design-based education
and workforce development initiatives through training content and
courses across several global universities, the Google-SkyWater
shuttles also
includes GlobalFoundries shuttles, design contests and IC design
workshops. The OpenROAD flow has been successfully used to date
in over 600 silicon-ready tapeouts for technologies up to 12nm.
## Getting Started with OpenROAD-flow-scripts
OpenROAD provides OpenROAD-flow-scripts
as a native, ready-to-use prototyping and tapeout flow. However,
it also enables the creation of any custom flow controllers based
on the underlying tools, database and analysis engines. Please refer to the flow documentation here.
OpenROAD-flow-scripts (ORFS) is a fully autonomous, RTL-GDSII flow
for rapid architecture and design space exploration, early prediction
of QoR and detailed physical design implementation. However, ORFS
also enables manual intervention for finer user control of individual
flow stages through Tcl commands and Python APIs.
Figure below shows the main stages of the OpenROAD-flow-scripts:
 [code] 
Here are the main steps for a physical design implementation
using OpenROAD;
- `Floorplanning`
 - Floorplan initialization - define the chip area, utilization
 - IO pin placement (for designs without pads)
 - Tap cell and well tie insertion
 - PDN- power distribution network creation
- `Global Placement` 
 - Macro placement (RAMs, embedded macros)
 - Standard cell placement
 - Automatic placement optimization and repair for max slew,
 max capacitance, and max fanout violations and long wires
- `Detailed Placement`
 - Legalize placement - align to grid, adhere to design rules
 - Incremental timing analysis for early estimates
- `Clock Tree Synthesis` 
 - Insert buffers and resize for high fanout nets
- `Optimize setup/ho