getwud / wud

Keep your containers up-to-date!

RogueUntoYeti / eft-dma-radar-rpocket

PCIe DMA-based external game state reader. Hardware DMA capture, memory layout discovery, no in-process injection. C#

verilator / verilator

Verilator open-source SystemVerilog simulator and lint system

lowRISC / ibex

Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)

semantic-release / semantic-release

📦🚀 Fully automated version management and package publishing

remvze / moodist

Ambient sounds for focus and calm.

Tencent / wave-mcp

Open-source, license-free MCP server for RTL waveform debug: reads FST waveforms (VCD/FSDB auto-convert) plus a SystemVerilog netlist, with 34 tools covering driver analysis, value/X tracing, pass-fail waveform diff, a browser wave viewer the agent drives, and pre-simulation static analysis.

obi1kenobi / cargo-semver-checks

Scan your Rust crate for semver violations.

openhwfoundation / cva6

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

chipsalliance / verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

MikePopoloski / slang

SystemVerilog compiler and language services

openhwfoundation / cvw

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

commitizen-tools / commitizen

Create committing rules for projects :rocket: auto bump versions :arrow_up: and auto changelog generation :open_file_folder:

pulp-platform / axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

TerosTechnology / vscode-terosHDL

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

7h30th3r0n3 / Flipper-EvilRelay

ISO-DEP (ISO 14443-4) NFC relay for the Flipper Zero. Read a real contactless card on a phone/Evil-Cardputer, relay APDUs over Wi-Fi to an ESP32-C3 bridge, and emulate the card to the reader with the Flipper. Ported from Evil-M5Project.

jaywcjlove / reference

面向开发者的技术速查清单（Cheat Sheets）集合，整理常见技术、工具与开发流程，帮助快速查阅关键信息，提高开发效率。

release-it / release-it

🚀 Automate versioning and package publishing

npm / node-semver

The semver parser for node (the one npm uses)

python-semantic-release / python-semantic-release

Automating Releases via SemVer and Commit Message Conventions

veryl-lang / veryl

Veryl: A Modern Hardware Description Language

nand2mario / z486_MiSTer

z486 MiSTer core

OpenBMB / SimpleMemVLA

Native-video memory for vision-language-action models, using timestamped visual history and exact streaming inference for long-horizon robot manipulation.

clash-lang / clash-compiler

Haskell to VHDL/Verilog/SystemVerilog compiler

divertimentos / Curso-Python-Gustavo-Guanabara

Mais de 100 exercícios resolvidos do curso de fundamentos de Python 3, ministrado pelo prof. Gustavo Guanabara do Curso em Vídeo.

openhwfoundation / core-v-verif

Functional verification project for the CORE-V family of RISC-V cores.

semver / semver.org

Semantic Versioning spec and website

python-semver / python-semver

Python package to work with Semantic Versioning (https://semver.org/)

haruto89610 / rtl-nic

Source-available SystemVerilog RTL for a custom FPGA Ethernet datapath with ARP, IPv4, UDP, and specialized TCP transport control.

qingxuanxx / sv_uvm_axi_notes

数字IC验证学习笔记：SV/UVM/AMBA总线（AXI/APB/AHB/AXI-Lite/AXI-Stream）+ 数字IC验证校招面经

keel-hq / keel

Kubernetes Operator to automate Helm, DaemonSet, StatefulSet & Deployment updates

VUnit / vunit

VUnit is a unit testing framework for VHDL/SystemVerilog

jscutlery / semver

Nx plugin to automate semantic versioning and CHANGELOG generation.

mathieudutour / github-tag-action

A Github Action to automatically bump and tag master, on merge, with the latest SemVer formatted version. Works on any platform.

bespoke-silicon-group / basejump_stl

BaseJump STL: A Standard Template Library for SystemVerilog

absolute-version / commit-and-tag-version

Current fork of the excellent standard-version. Automate versioning and CHANGELOG generation, with semver.org and conventionalcommits.org :trophy:

devlooped / GitInfo

Git and SemVer Info from MSBuild, C# and VB

dalance / svls

SystemVerilog language server

cargo-public-api / cargo-public-api

List and diff the public API of Rust library crates between releases and commits. Detect breaking API changes and semver violations via CI or a CLI.

chipsalliance / caliptra-rtl

HW Design Collateral for Caliptra RoT IP

chipsalliance / caliptra-ss

HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.

sauravsingla / MemVanta

Low-memory C++20 LLM inference runtime for quantized GGUF models on CPU — mmap-backed weights, paged KV cache, Q4/Q8 kernels, and reproducible llama.cpp benchmarks.

adibis / brokenBench

Systemverilog and UVM exercises inspired by ziglings

nand2mario / zSST

Voodoo-1 3D graphics chipset in SystemVerilog

nand2mario / z486

80486-class CPU with integrated floating-point in SystemVerilog

JamieMason / syncpack

Consistent dependency versions in large JavaScript Monorepos.

microsoft / beachball

The Sunniest Semantic Version Bumper

SweiryDev / MicroCNN-TangNano20k

SystemVerilog SoC implementing MicroCNN accelerator on the Tang Nano 20K for BloodMNIST image classification.

composer / semver

Semantic versioning utilities with the addition of version constraints parsing and checking.

GitTools / GitVersion

From git log to SemVer in no time

liujianyu20021122 / RTL-ASS

Codex-first, vendor-neutral RTL coding and verification skill using open-source tools

orhun / git-cliff

A highly customizable Changelog Generator that follows Conventional Commit specifications ⛰️