lowRISC / ibex

Ibex OpenTitan configuration Nightly Regression
# Ibex RISC-V Core
Ibex is a production-quality open source 32-bit RISC-V CPU core written in
SystemVerilog. The CPU core is heavily parametrizable and well suited for
embedded control applications. Ibex is being extensively verified and has
seen multiple tape-outs. Ibex supports the Integer (I) or Embedded (E),
Integer Multiplication and Division (M), Compressed (C), and B (Bit
Manipulation) extensions.
Ibex was initially developed as part of the PULP platform
under the name "Zero-riscy", and has been
contributed to lowRISC who maintains it and develops it further. It is
under active development.
## Configuration
Ibex offers several configuration parameters to meet the needs of various application scenarios.
The options include different choices for the architecture of the multiplier unit, as well as a range of performance and security features.
The table below indicates performance, area and verification status for a few selected configurations.
These are configurations on which lowRISC is focusing for performance evaluation and design verification (see supported configs).
| Config | "micro" | "small" | "maxperf" | "maxperf-pmp-bmfull" |
| ------ | ------- | --------| ----------| -------------------- |
| Features | RV32EC | RV32IMC, 3 cycle mult | RV32IMC, 1 cycle mult, Branch target ALU, Writeback stage | RV32IMCB, 1 cycle mult, Branch target ALU, Writeback stage, 16 PMP regions |
| Performance (CoreMark/MHz) | 0.904 | 2.47 | 3.13 | 3.13 |
| Area - Yosys (kGE) | 16.85 | 26.60 | 32.48 | 66.02 |
| Area - Commercial (estimated kGE) | ~15 | ~24 | ~30 | ~61 |
| Verification status | Red | Green | Green | Green |
Notes:
* Performance numbers are based on CoreMark running on the Ibex Simple System platform.
 Note that different ISAs (use of B and C extensions) give the best results for different configurations.
 See the Benchmarks README for more information.
* Yosys synthesis area numbers are based on the Ibex basic synthesis flow using the latch-based register file.
* Commercial synthesis area numbers are a rough estimate of what might be achievable with a commercial synthesis flow and technology library.
* For comparison, the original "Zero-riscy" core yields an area of 23.14kGE using our Yosys synthesis flow.
* Verification status is a rough guide to the overall maturity of a particular configuration.
 Green indicates that verification is close to complete.
 Amber indicates that some verification has been performed, but the configuration is still experimental.
 Red indicates a configuration with minimal/no verification.
 Users must make their own assessment of verification readiness for any tapeout.
* The ratified v.1.0.0 RISC-V Bit-Manipulation Extension (Zba, Zbb, Zbc, Zbs) is supported, as well as the ratified Zbkb and Zbkx sub-extensions of the RISC-V Scalar Cryptography Extension.
 See Standards Compliance in the Ibex documentation for more information.
## Documentation
The Ibex user manual can