chipsalliance / caliptra-ss
git clone https://github.com/chipsalliance/caliptra-ss.git
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SystemVerilog hardware design collateral for the Caliptra Subsystem, a root-of-trust IP plus manufacturer control infrastructure.
Why you might care
Provides the open RTL and verification/integration assets for the Caliptra RoT subsystem, intended for silicon integrators building OCP-aligned hardware root of trust. Consume releases by tag rather than the attached assets or main branch; tooling requires commercial EDA flows such as VCS and SpyGlass.
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64
forks · 122 open issues
Star history (as recorded here)
LanguageSystemVerilog
LicenseApache-2.0
Created2024-01-24 (2y ago)
Last pushtoday
Watchers18
OwnerOrganization
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