Lightweight Armoury Crate alternative for Asus laptops with nearly the same functionality. Works with ROG Zephyrus, Flow, TUF, Strix, Scar, ProArt, Vivobook, Zenbook, Expertbook, ROG Ally, and more.
ArduPlane, ArduCopter, ArduRover, ArduSub source
Espressif IoT Development Framework. Official development framework for Espressif SoCs.
Primary Git Repository for the Zephyr Project. Zephyr is a new generation, scalable, optimized, secure RTOS for multiple hardware architectures.
Libre Hardware Monitor is free software that can monitor the temperature sensors, fan speeds, voltages, load and clock speeds of your computer.
Linux Kernel for Surface Devices
A minimal GPU design in Verilog to learn how GPUs work from the ground up
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
Open-source high-performance RISC-V processor
An open source cross-platform USB stack for embedded system
Berkeley's Spatial Array Generator
Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)
Firmware modification for MediaTek MT1959-based Hitachi-LG optical drives that enables lead-in/lead-out and raw sector reading of discs.
OpenTitan: Open source silicon root of trust
Amiga Minimig ported to the Tang Nano 20k FPGA
The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.
CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
NixOS module for NVIDIA Jetson devices
The Swiss army knife of vanilla Hackintoshing
Submission template for Tiny Tapeout SKY130 (ChipFoundry) shuttles - Verilog HDL Projects
RISC-V Instruction Set Manual
z486 MiSTer core
BLHeli for brushless ESC firmware
The RISC-V Architectural Certification Tests (ACTs) are a set of assembly language tests designed to certify that a design faithfully implements the RISC-V specification.
VHDL 2008/93/87 simulator
The USRPβ’ Hardware Driver Repository
HW Design Collateral for Caliptra RoT IP
HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.
Energy Exascale Earth System Model source code. NOTE: use "maint" branches for your work. Head of master is not validated.
NekokoLPA2