OpenXiangShan / XiangShan

# XiangShan
XiangShan (香山) is an open-source high-performance RISC-V processor project.
English | 中文
## Documentation
XiangShan's documentation is available at docs.xiangshan.cc.
XiangShan Design Document for Kunminghu V2R2 has been published separately. You can find it at docs.xiangshan.cc/projects/design.
XiangShan User Guide has been published separately. You can find it at docs.xiangshan.cc/projects/user-guide or XiangShan-User-Guide/releases.
We are using Weblate to translate documentation into English and other languages. Your contributions are welcome—come and help us improve it!
All XiangShan documents are licensed under the CC-BY-4.0.
## Publications
### MICRO 2022: Towards Developing High Performance RISC-V Processors Using Agile Methodology
Our paper introduces XiangShan and the practice of agile development methodology on high performance RISC-V processors.
It covers some representative tools we have developed and used to accelerate the chip development process, including design, functional verification, debugging, performance validation, etc.
This paper is awarded all three available badges for artifact evaluation (Available, Functional, and Reproduced).
Paper PDF | IEEE Xplore | BibTeX | Presentation Slides | Presentation Video
## Follow us
Wechat/微信：香山开源处理器
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Weibo/微博：香山开源处理器
You can contact us through our mailing list. All mails from this list will be archived here.
## Architecture
The first stable micro-architecture of XiangShan is called Yanqihu (雁栖湖) and is on the yanqihu branch, which has been developed since June 2020.
The second stable micro-architecture of XiangShan is called Nanhu (南湖) and is on the nanhu branch.
The third-generation XiangShan microarchitecture, Kunminghu (昆明湖), is under active development on the `kunminghu-v2` and `kunminghu-v3` branches.
The micro-architecture overview of Kunminghu-V2 is shown below.
## Branch Maintenance Status
| Generation-Version | Branch | Maintained? | Active Development? |
| ------------------ | --------------------------------------------------------------------------------------- | ------------ | ------------------- |
| Yanqihu | yanqihu | ✅ (minimum) | |
| Nanhu-V2 | nanhu | ✅ (minimum) | |
| Nanhu-V3 | Siudya/Nanhu | | |
| Nanhu-V5 | OpenXiangShan-Nanhu/OpenNanhu-V5 | ✅ | ✅ |
| Kunminghu-V2 | kunminghu-v2 | ✅ | |
| Kunminghu-V3 | kunminghu-v3 | ✅ | ✅ |
At the moment, `kunminghu-v3` is still evolving rapidly and its functionality may not yet be stable. If you plan to use XiangShan for research, verification, or downstream applications, we recommend prioritizing `kunminghu-v2`.
This section is time-sensitive. If you believe any information here is outdated, please let us know in an issue and we will update it as soon as possible.
Last updated: 2026/06/30
## Sub-directories Overview
Some of the key directories are shown below.
 [code] 
## IDE Support
### bsp
 [code] 
### IDEA
 [code] 
## Generate Verilog
* Run `make verilog` to generate verilog code. This generates