raysan5 / raylib
A C library for videogame programming with 2D/3D graphics, input, audio, and windowing across desktop, mobile, web, and embedded platforms.
raysan5 / raylib
theorem-labs / oss-verify-proofs
Theorem statements about OSS-Fuzz fuzz targets as compiled RISC-V binaries, and machine-checked Rocq proofs of them
Limine-Bootloader / Limine
Modern, secure, portable, multiprotocol bootloader and boot manager.
Tencent / ncnn
ncnn is a high-performance neural network inference framework optimized for the mobile platform
mit-pdos / xv6-riscv
A teaching operating system: a re-implementation of Unix Version 6 in ANSI C for RISC-V multiprocessors, running on QEMU.
capstone-engine / capstone
Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), Alpha, BPF, Ethereum VM, HPPA, LoongArch, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriCore, Webassembly, XCore and X86.
THU-DSP-LAB / ventus-gpgpu
GPGPU processor supporting RISCV-V extension, developed with Chisel HDL
ucb-bar / chipyard
Open-source Chisel framework for building agile RISC-V systems-on-chip from cores, accelerators, and peripherals.
riscv / learn
Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.
LekKit / RVVM
The RISC-V Virtual Machine
pbatard / UEFI-Shell
UEFI Shell binary images, generated from EDK2 stable
unicorn-engine / unicorn
Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)
chipsalliance / rocket-chip
Rocket Chip Generator
tlack / babytalk
Optimized ESP32-S3/P4 fully offline speech to text and text to speech system for Micropython and AtomVM, featuring a finetuned STT model for noisy environments, plus a data generation/field capture/model finetuning framework. Includes high performance 4/8bit int kernels for Xtensa/RiscV PIE vector units
SpinalHDL / VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation
riscv-software-src / riscv-isa-sim
Spike, a RISC-V ISA Simulator
riscv-mcu / e203_hbirdv2
The Ultra-Low Power RISC-V Core
riscv-software-src / opensbi
RISC-V Open Source Supervisor Binary Interface
mit-pdos / xv6-riscv-book
Text describing xv6 on RISC-V
fnuecke / oc2
RISC-V and Z80 VMs and peripherals in Minecraft
riscv / riscv-arch-test
The RISC-V Architectural Certification Tests (ACTs) are a set of assembly language tests designed to certify that a design faithfully implements the RISC-V specification.
riscv / riscv-isa-manual
Source files for the RISC-V Instruction Set Manual, the formal specification of the RISC-V unprivileged, privileged, and profiles architecture.
probe-rs / probe-rs
A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host
earlephilhower / arduino-pico
Raspberry Pi Pico Arduino core, for all RP2040 and RP2350 boards
riscv-boom / riscv-boom
SonicBOOM: The Berkeley Out-of-Order Machine
rustsbi / rustsbi
RISC-V Supervisor Binary Interface (RISC-V SBI) library in Rust; runs on M or HS mode; good support for embedded Rust ecosystem. For binary download see firmware folder.
openhwfoundation / cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
riscv / sail-riscv
Sail RISC-V model
litex-hub / linux-on-litex-vexriscv
Linux on LiteX-VexRiscv
pulp-platform / ara
The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
riscv-collab / riscv-gnu-toolchain
GNU toolchain for RISC-V, including GCC
darklife / darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
cyring / CoreFreq
CoreFreq : CPU monitoring and tuning software designed for the 64-bit processors.
o8vm / octox
Unix-like OS in Rust inspired by xv6-riscv
riscv-non-isa / riscv-asm-manual
RISC-V Assembly Programmer's Manual
sysprog21 / shecc
A self-hosting and educational C optimizing compiler
rust-embedded / riscv
Low level access to RISC-V processors
libriscv / libriscv
The fastest RVA23 RISC-V sandbox
riscv / riscv-opcodes
RISC-V Opcodes
riscv-non-isa / riscv-elf-psabi-doc
A RISC-V ELF psABI Document
uraimo / run-on-arch-action
A Github Action that executes jobs/commands on non-x86 cpu architectures (ARMv6, ARMv7, aarch64, s390x, ppc64le, riscv64) via QEMU
sysprog21 / rv32emu
Compact and Efficient RISC-V RV32I[MAFC] emulator
pieroproietti / penguins-eggs-legacy
A professional and universal remastering tool for all major distributions
tyfkda / xcc
Standalone C compiler/assembler/linker/libc for x86-64/aarch64/riscv64/wasm
tsuyoshi-otake / m5stamp-p4-c6-linux
Native RISC-V NOMMU Linux 7.2 (dual-core SMP) with SDIO Wi-Fi (ESP-Hosted-NG), Dropbear SSH and MicroPython for M5Stack Stamp-P4 + Stamp-AddOn C6
b3s3da / qemu-harness
QEMU harness for AI agents: boot aarch64/arm/riscv64/x86_64 kernels in seconds, exec via guest agent, fast rootfs rebuilds, IoT emulation
riscv-software-src / riscv-tests
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vnmakarov / mir
A lightweight JIT compiler based on MIR (Medium Internal Representation) and C11 JIT compiler and interpreter based on MIR
jonathansong / Torch2RISCV-accelerator
An end-to-end compiler stack that lowers PyTorch models to a custom RISC-V instruction set, running on a heterogeneous **ARM (host) + PicoRV32 (control core) + systolic-array accelerator** built on a PYNQ-Z1 board.