raysan5 / raylib
A simple and easy-to-use library to enjoy videogames programming
raysan5 / raylib
OpenXiangShan / XiangShan
Open-source high-performance RISC-V processor
lowRISC / ibex
Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)
lowRISC / opentitan
OpenTitan: Open source silicon root of trust
openhwfoundation / cvw
CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
simdjson / simdjson
Parsing gigabytes of JSON per second : used by Facebook/Meta Velox, the Node.js runtime, ClickHouse, WatermelonDB, Apache Doris, Milvus, StarRocks
Tencent / ncnn
ncnn is a high-performance neural network inference framework optimized for the mobile platform
k2-fsa / sherpa-onnx
Speech-to-text, text-to-speech, speaker diarization, speech enhancement, source separation, and VAD using next-gen Kaldi with onnxruntime without Internet connection. Support embedded systems, Android, iOS, HarmonyOS, Raspberry Pi, RISC-V, RK NPU, Axera NPU, Ascend NPU, x86_64 servers, websocket server/client, support 12 programming languages
mytechnotalent / Reverse-Engineering
A FREE comprehensive reverse engineering tutorial covering x86, x64, 32-bit/64-bit ARM, 8-bit AVR and 32-bit RISC-V architectures.
RT-Thread / rt-thread
RT-Thread is an open source IoT Real-Time Operating System (RTOS). https://rt-thread.github.io/rt-thread/
mit-pdos / xv6-riscv
Xv6 for RISC-V
platformio / platformio-core
Your Gateway to Embedded Software Development Excellence :alien:
unicorn-engine / unicorn
Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)
capstone-engine / capstone
Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), Alpha, BPF, Ethereum VM, HPPA, LoongArch, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriCore, Webassembly, XCore and X86.
sipeed / NanoKVM
Affordable, Multifunctional, Nano RISC-V IP-KVM
tock / tock
A secure embedded operating system for microcontrollers
MichaIng / DietPi
Lightweight justice for your single-board computer!
riscv / riscv-isa-manual
RISC-V Instruction Set Manual
riscv-collab / riscv-gnu-toolchain
GNU toolchain for RISC-V, including GCC
uxlfoundation / oneDNN
Open-source library of optimized deep learning operations (matmul, convolution, attention) for CPUs (x64, AArch64, RISC-V) and Intel GPUs. Used by PyTorch, TensorFlow, OpenVINO, and ONNX Runtime.
Limine-Bootloader / Limine
Modern, secure, portable, multiprotocol bootloader and boot manager.
mortbopet / Ripes
A graphical processor simulator and assembly editor for the RISC-V ISA
SpinalHDL / VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation
riscv-software-src / riscv-isa-sim
Spike, a RISC-V ISA Simulator
mriscoc / Ender3V2S1
This is optimized firmware for Ender3 V2/S1 3D printers.
openhwfoundation / cva6
The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.
renode / renode
Renode - Antmicro's open source simulation and virtual development framework for complex embedded systems
probe-rs / probe-rs
A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host
earlephilhower / arduino-pico
Raspberry Pi Pico Arduino core, for all RP2040 and RP2350 boards
gem5 / gem5
The official repository for the gem5 computer-system architecture simulator.
xtensor-stack / xsimd
C++ wrappers for SIMD intrinsics and parallelized, optimized mathematical functions (SSE, AVX, AVX512, NEON, SVE, WebAssembly, VSX, RISC-V))
darklife / darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
uxmal / reko
Reko is a binary decompiler.
cksystemsteaching / selfie
An educational software system of a tiny self-compiling C compiler, a tiny self-executing RISC-V emulator, and a tiny self-hosting RISC-V hypervisor.
ucb-bar / chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
stnolting / neorv32
🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
riscv-boom / riscv-boom
SonicBOOM: The Berkeley Out-of-Order Machine
cyring / CoreFreq
CoreFreq : CPU monitoring and tuning software designed for the 64-bit processors.
ipxe / ipxe
iPXE network bootloader
simdutf / simdutf
Unicode routines (UTF8, UTF16, UTF32) and Base64: billions of characters per second using SSE2, AVX2, NEON, AVX-512, RISC-V Vector Extension, LoongArch64, POWER. Part of Node.js, WebKit/Safari, Ladybird, Chromium, Cloudflare Workers, Ghostty and Bun.
riscv-mcu / e203_hbirdv2
The Ultra-Low Power RISC-V Core
kfrlib / kfr
Fast, modern C++ DSP framework, FFT, Sample Rate Conversion, FIR/IIR/Biquad Filters (SSE, AVX, AVX-512, ARM NEON, RISC-V RVV)
o8vm / octox
Unix-like OS in Rust inspired by xv6-riscv
ashvardanian / NumKong
SIMD-accelerated distances, dot products, matrix ops, geospatial & geometric kernels for 16 numeric types — from 6-bit floats to 64-bit complex — across x86, Arm, RISC-V, and WASM, with bindings for Python, Rust, C, C++, Swift, JS, and Go 📐
riscv / learn
Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.
succinctlabs / sp1
SP1 is a zero‑knowledge virtual machine that proves the correct execution of programs compiled for the RISC-V architecture.
riscv-non-isa / riscv-asm-manual
RISC-V Assembly Programmer's Manual
cnlohr / ch32fun
Open source minimal stack for the ch32 and ch5xx WCH RISC-V Microcontrollers
OSCPU / NutShell
RISC-V SoC designed by students in UCAS
riscv-software-src / opensbi
RISC-V Open Source Supervisor Binary Interface
sysprog21 / shecc
A self-hosting and educational C optimizing compiler
chili-chips-ba / wireguard-fpga
Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door is wide open for backdoor scrutiny, be it related to RTL, embedded, build, bitstream or any other aspect of design and delivery package. Bujrum!
chipsalliance / riscv-dv
Random instruction generator for RISC-V processor verification
rustsbi / rustsbi
RISC-V Supervisor Binary Interface (RISC-V SBI) library in Rust; runs on M or HS mode; good support for embedded Rust ecosystem. For binary download see firmware folder.
openhwfoundation / cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
LekKit / RVVM
The RISC-V Virtual Machine
riscv-software-src / riscv-tests
—
rsd-devel / rsd
RSD: RISC-V Out-of-Order Superscalar Processor
TomHarte / CLK
A latency-hating emulator of: the Acorn Electron, BBC Micro and Archimedes, Amstrad CPC, Apple II/II+/IIe and early Macintosh, Atari 2600 and ST, ColecoVision, Enterprise 64/128, Commodore Vic-20 and Amiga, MSX 1/2, Oric 1/Atmos, early PC compatibles, Sega Master System, Sinclair ZX80/81 and ZX Spectrum, Tandy CoCo and Thomson MO5/6.
rust-embedded / riscv
Low level access to RISC-V processors