verilator / verilator

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Welcome to Verilator
====================
.. list-table::
 - - **Welcome to Verilator, the fastest Verilog/SystemVerilog simulator.**
 - Accepts Verilog or SystemVerilog, including UVM
 - Performs lint code-quality checks
 - Compiles into multithreaded C++, or SystemC
 - Creates JSON to front-end your own tools
 - |Logo|
 - - |verilator multithreaded performance|
 - **Fast**
 - Outperforms many closed-source commercial simulators
 - Single- and multithreaded output models
 - - **Widely Used**
 - Wide industry and academic deployment
 - Out-of-the-box support from Arm and RISC-V vendor IP
 - Over 700 contributors
 - |verilator usage|
 - - |verilator community|
 - **Community Driven & Openly Licensed**
 - Guided by the `CHIPS Alliance`_ and `Linux Foundation`_
 - Open, and free as in both speech and beer
 - More simulation for your verification budget
 - - **Commercial Support Available**
 - Commercial support contracts
 - Design support contracts
 - Enhancement contracts
 - |verilator support|
What Verilator Does
===================
Verilator is invoked with parameters similar to GCC or Synopsys's VCS. It
"Verilates" the specified Verilog or SystemVerilog code by reading it,
performing lint checks, and optionally inserting assertion checks and
coverage-analysis points. It outputs single- or multithreaded .cpp and .h
files, the "Verilated" code.
Verilator can automatically generate a simulator executable (using
``--binary``), or users can write their own C++/SystemC wrapper to
instantiate the model. The resulting Verilated executable performs the
design simulation. Verilator