logisim-evolution / logisim-evolution

Digital logic design tool and simulator

SpinalHDL / VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation

openhwfoundation / cva6

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

ps2homebrew / Open-PS2-Loader

Game and app loader for Sony PlayStation 2

cocotb / cocotb

cocotb: Python-based chip (RTL) verification

SpinalHDL / SpinalHDL

Scala based HDL

clash-lang / clash-compiler

Haskell to VHDL/Verilog/SystemVerilog compiler

ghdl / ghdl

VHDL 2008/93/87 simulator

langhuihui / monibuca

🧩 Monibuca is a Modularized, Extensible framework for building Streaming Server

stnolting / neorv32

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

analogdevicesinc / hdl

HDL libraries and projects

olofk / fusesoc

Package manager and build abstraction tool for FPGA/ASIC development

siliconcompiler / siliconcompiler

Modular hardware build system

Digital-EDA / Digital-IDE

All in one vscode plugin for HDL development

veryl-lang / veryl

Veryl: A Modern Hardware Description Language

THU-DSP-LAB / ventus-gpgpu

GPGPU processor supporting RISCV-V extension, developed with Chisel HDL

open-sdr / openwifi-hw

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

nickg / nvc

VHDL compiler and simulator

VUnit / vunit

VUnit is a unit testing framework for VHDL/SystemVerilog

JulianKemmerer / PipelineC

PypelineC: A hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

TerosTechnology / vscode-terosHDL

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

VHDL-LS / rust_hdl

A fast VHDL language server and analysis library written in Rust

StefanSchippers / xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

oscar30gt / pulse

Pulse is a multi-platform digital logic simulation engine for VHDL made with C++. It transforms VHDL source code into logic components so it can be simulated and debugged.

TinyTapeout / ttsky-verilog-template

Submission template for Tiny Tapeout SKY130 (ChipFoundry) shuttles - Verilog HDL Projects

Nero7991 / llm.vhdl

Full-fabric VHDL Qwen3.5 9B/ Qwen3.8 27B LLM inference engine on XCVU33P/XCVU35P