raysan5 / raylib

A simple and easy-to-use library to enjoy videogames programming

k2-fsa / sherpa-onnx

Speech-to-text, text-to-speech, speaker diarization, speech enhancement, source separation, and VAD using next-gen Kaldi with onnxruntime without Internet connection. Support embedded systems, Android, iOS, HarmonyOS, Raspberry Pi, RISC-V, RK NPU, Axera NPU, Ascend NPU, x86_64 servers, websocket server/client, support 12 programming languages

theorem-labs / oss-verify-proofs

Theorem statements about OSS-Fuzz fuzz targets as compiled RISC-V binaries, and machine-checked Rocq proofs of them

mytechnotalent / Reverse-Engineering

A FREE comprehensive reverse engineering tutorial covering x86, x64, 32-bit/64-bit ARM, 8-bit AVR and 32-bit RISC-V architectures.

theorem-labs / oss-verify

OSS Verify: enrollment and build instructions for formally verifying open-source fuzz targets

theorem-labs / rocq-linux-process-semantics

A Rocq model of a Linux process that runs a RISC-V binary

OpenXiangShan / XiangShan

Open-source high-performance RISC-V processor

platformio / platformio-core

Your Gateway to Embedded Software Development Excellence :alien:

MichaIng / DietPi

Lightweight justice for your single-board computer!

RT-Thread / rt-thread

RT-Thread is an open source IoT Real-Time Operating System (RTOS). https://rt-thread.github.io/rt-thread/

mit-pdos / xv6-riscv

Xv6 for RISC-V

capstone-engine / capstone

Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), Alpha, BPF, Ethereum VM, HPPA, LoongArch, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriCore, Webassembly, XCore and X86.

simdjson / simdjson

Parsing gigabytes of JSON per second : used by Facebook/Meta Velox, the Node.js runtime, ClickHouse, WatermelonDB, Apache Doris, Milvus, StarRocks

Limine-Bootloader / Limine

Modern, secure, portable, multiprotocol bootloader and boot manager.

lowRISC / ibex

Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)

Tencent / ncnn

ncnn is a high-performance neural network inference framework optimized for the mobile platform

renode / renode

Renode - Antmicro's open source simulation and virtual development framework for complex embedded systems

uxlfoundation / oneDNN

Open-source library of optimized deep learning operations (matmul, convolution, attention) for CPUs (x64, AArch64, RISC-V) and Intel GPUs. Used by PyTorch, TensorFlow, OpenVINO, and ONNX Runtime.

jonathansong / Torch2RISCV-accelerator

An end-to-end compiler stack that lowers PyTorch models to a custom RISC-V instruction set, running on a heterogeneous **ARM (host) + PicoRV32 (control core) + systolic-array accelerator** built on a PYNQ-Z1 board.

ucb-bar / chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

riscv / learn

Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.

unicorn-engine / unicorn

Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)

lowRISC / opentitan

OpenTitan: Open source silicon root of trust

THU-DSP-LAB / ventus-gpgpu

GPGPU processor supporting RISCV-V extension, developed with Chisel HDL

pbatard / UEFI-Shell

UEFI Shell binary images, generated from EDK2 stable

tock / tock

A secure embedded operating system for microcontrollers

chipsalliance / rocket-chip

Rocket Chip Generator

mriscoc / Ender3V2S1

This is optimized firmware for Ender3 V2/S1 3D printers.

openhwfoundation / cva6

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

gem5 / gem5

The official repository for the gem5 computer-system architecture simulator.

vnmakarov / mir

A lightweight JIT compiler based on MIR (Medium Internal Representation) and C11 JIT compiler and interpreter based on MIR

LekKit / RVVM

The RISC-V Virtual Machine

mit-pdos / xv6-riscv-book

Text describing xv6 on RISC-V

openhwfoundation / cvw

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

tlack / babytalk

Optimized ESP32-S3/P4 fully offline speech to text and text to speech system for Micropython and AtomVM, featuring a finetuned STT model for noisy environments, plus a data generation/field capture/model finetuning framework. Includes high performance 4/8bit int kernels for Xtensa/RiscV PIE vector units

sipeed / NanoKVM

Affordable, Multifunctional, Nano RISC-V IP-KVM

mortbopet / Ripes

A graphical processor simulator and assembly editor for the RISC-V ISA

SpinalHDL / VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation

uxmal / reko

Reko is a binary decompiler.

riscv-boom / riscv-boom

SonicBOOM: The Berkeley Out-of-Order Machine

freelawproject / juriscraper

An API to scrape American court websites for metadata.

munetomo-maruyama / mmRISC-2

64-bit RISC-V (RV64GC) core that boots Linux on an Arty A7 FPGA. Designed entirely by Claude Code: the specifications, RTL, verification and documents were all written by the AI.

riscv / riscv-isa-manual

RISC-V Instruction Set Manual

riscv-software-src / riscv-isa-sim

Spike, a RISC-V ISA Simulator

probe-rs / probe-rs

A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host

cksystemsteaching / selfie

An educational software system of a tiny self-compiling C compiler, a tiny self-executing RISC-V emulator, and a tiny self-hosting RISC-V hypervisor.

stnolting / neorv32

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

ipxe / ipxe

iPXE network bootloader

simdutf / simdutf

Unicode routines (UTF8, UTF16, UTF32) and Base64: billions of characters per second using SSE2, AVX2, NEON, AVX-512, RISC-V Vector Extension, LoongArch64, POWER. Part of Node.js, WebKit/Safari, Ladybird, Chromium, Cloudflare Workers, Ghostty and Bun.

riscv-mcu / e203_hbirdv2

The Ultra-Low Power RISC-V Core

succinctlabs / sp1

SP1 is a zero‑knowledge virtual machine that proves the correct execution of programs compiled for the RISC-V architecture.

cnlohr / ch32fun

Open source minimal stack for the ch32 and ch5xx WCH RISC-V Microcontrollers

riscv-software-src / opensbi

RISC-V Open Source Supervisor Binary Interface

chipsalliance / riscv-dv

Random instruction generator for RISC-V processor verification

TomHarte / CLK

A latency-hating emulator of: the Acorn Electron, BBC Micro and Archimedes, Amstrad CPC, Apple II/II+/IIe and early Macintosh, Atari 2600 and ST, ColecoVision, Enterprise 64/128, Commodore Vic-20 and Amiga, MSX 1/2, Oric 1/Atmos, early PC compatibles, Sega Master System, Sinclair ZX80/81 and ZX Spectrum, Tandy CoCo and Thomson MO5/6.

OFFTKP / felix86

Run x86 and x86-64 games on RISC‑V Linux

fnuecke / oc2

RISC-V and Z80 VMs and peripherals in Minecraft

pulp-platform / ara

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

dormancygrace / NanoKVM-OS

Community firmware for NanoKVM: 4K video, WebRTC and Direct streaming, USB virtual media and networking, VPNs and add-ons. Alpine Linux with signed updates. Independent of Sipeed.

riscv / riscv-arch-test

The RISC-V Architectural Certification Tests (ACTs) are a set of assembly language tests designed to certify that a design faithfully implements the RISC-V specification.