Open-source ESP32 firmware that turns a board into a multi-protocol hardware hacking tool with a serial or web-based CLI.
Windows utility for controlling Asus laptop performance modes, fans, GPU mode, keyboard lighting, and battery settings.
Open-source mini quadruped robot built on an ESP32, with 3D-printable parts, 8 servos, and an OLED face.
macOS menu bar app that reports in plain English what each USB-C cable on your Mac can do and why charging may be slow.
Patched Linux kernel and support packages that add drivers for Microsoft Surface hardware not yet upstream.
Open-source unified application implementing an RTL-to-GDS physical design flow for digital chips, with Tcl and Python APIs.
A minimal GPU design written in Verilog that shows how GPU cores, dispatch, and memory controllers work together.
Open source LoRa-based radio control link firmware for FPV drones and RC vehicles, running on ESP and STM32 hardware.
Open-source firmware for custom keyboard controllers, supporting AVR and Arm USB microcontrollers and many keyboard designs.
Open-source high-performance RISC-V processor core written in Chisel, developed by the XiangShan project.
Ibex is a parametrizable 32-bit RISC-V CPU core written in SystemVerilog for embedded control applications.
Cross-platform USB host and device stack in C for embedded systems, with no dynamic allocation and interrupts deferred to task context.
Firmware modification for MediaTek MT1959-based Hitachi-LG optical drives that enables lead-in/lead-out and raw sector reading of discs.
Community payload library of DuckyScript keystroke-injection scripts for the Hak5 USB Rubber Ducky.
Open source silicon root of trust hardware, software, and tooling in a single monorepo, developed by lowRISC and partners.
FPGA port of the Minimig Amiga core for Tang Nano 20K, Primer 25K, Mega 138K Pro and other Tang and IcePi boards.
CVA6 is a 6-stage, single-issue, in-order 64-bit RISC-V CPU core written in SystemVerilog, supporting Linux-capable configurations.
Open-source Chisel framework for building agile RISC-V systems-on-chip from cores, accelerators, and peripherals.
Starter template for building Verilog designs that get fabricated on a Tiny Tapeout SKY130 shuttle chip.
Wally is a configurable 5-stage pipelined RISC-V processor written in SystemVerilog, supporting RVA22 and virtual memory.
Open-source assembly firmware for sensorless brushless motor speed controllers (ESCs) on Atmel and Silabs 8-bit MCUs.
Source files for the RISC-V Instruction Set Manual, the formal specification of the RISC-V unprivileged, privileged, and profiles architecture.