verilator / verilator
Verilator open-source SystemVerilog simulator and lint system
verilator / verilator
openhwfoundation / cva6
The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.
chipsalliance / verible
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
pulp-platform / axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
clash-lang / clash-compiler
Haskell to VHDL/Verilog/SystemVerilog compiler
MikePopoloski / slang
SystemVerilog compiler and language services
veryl-lang / veryl
Veryl: A Modern Hardware Description Language
VUnit / vunit
VUnit is a unit testing framework for VHDL/SystemVerilog
TerosTechnology / vscode-terosHDL
VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
openhwfoundation / core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
bespoke-silicon-group / basejump_stl
BaseJump STL: A Standard Template Library for SystemVerilog
dalance / svls
SystemVerilog language server
Tencent / wave-mcp
Open-source, license-free MCP server for RTL waveform debug: reads FST waveforms (VCD/FSDB auto-convert) plus a SystemVerilog netlist, with 34 tools covering driver analysis, value/X tracing, pass-fail waveform diff, a browser wave viewer the agent drives, and pre-simulation static analysis.
liujianyu20021122 / RTL-ASS
Codex-first, vendor-neutral RTL coding and verification skill using open-source tools
SweiryDev / MicroCNN-TangNano20k
SystemVerilog SoC implementing MicroCNN accelerator on the Tang Nano 20K for BloodMNIST image classification.
haruto89610 / rtl-nic
Source-available SystemVerilog RTL for a custom FPGA Ethernet datapath with ARP, IPv4, UDP, and specialized TCP transport control.
qingxuanxx / sv_uvm_axi_notes
数字IC验证学习笔记：SV/UVM/AMBA总线（AXI/APB/AHB/AXI-Lite/AXI-Stream）+ 数字IC验证校招面经
adibis / brokenBench
Systemverilog and UVM exercises inspired by ziglings
nand2mario / zSST
Voodoo-1 3D graphics chipset in SystemVerilog
nand2mario / z486
80486-class CPU with integrated floating-point in SystemVerilog