openecos-projects / icsprout55-pdk
git clone https://github.com/openecos-projects/icsprout55-pdk.git
v1.10.103 · 18d ago
Open-source 55nm CMOS process design kit with design rules, device models, standard cells, and parameterized cells for digital chip design.
Why you might care
Gives university and open-source designers a complete RTL-to-GDS backend path on a production 55nm process from ICsprout, covering synthesis, place and route, and physical verification. It is a preview release still undergoing silicon validation, and RAMs, SPICE models, and PDN are listed as todo.
+3
stars, 24h · #9,859
+15
stars, 7 days · #14,061
+~64
stars, 30 days · #13,172
328
★ total · +5% this week
34
forks · 11 open issues
Star history (as recorded here)
LanguageVerilog
LicenseApache-2.0
Created2025-10-21 (1y ago)
Last push2d ago
Watchers18
OwnerOrganization
Seen on GitHub Trending
- 2026-10-30 — #8 daily in verilog · +4 ★
- 2026-10-25 — #5 daily in verilog · +1 ★
GitHub topics
Links
- GitHub: github.com/openecos-projects/icsprout55-pdk
- Homepage: https://icsprout55-pdk.rtfd.io
- Releases · Issues · Hacker News mentions
README
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Blurb generated by claude-haiku-5-5 2d ago. Star deltas marked ~ are extrapolated from partial history.