lowRISC / ibex
git clone https://github.com/lowRISC/ibex.git
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Ibex is a parametrizable 32-bit RISC-V CPU core written in SystemVerilog for embedded control applications.
Why you might care
Suited for embedded hardware designers who need a small, configurable RISC-V core with extensive verification and multiple tape-outs. Supports RV32 I or E base with M, C, and B extensions, and offers configurable multiplier, PMP, and performance options.
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stars, 30 days · #9,933
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825
forks · 274 open issues
Star history (as recorded here)
LanguageSystemVerilog
LicenseApache-2.0
Created2017-08-08 (9y ago)
Last pushtoday
Watchers93
OwnerOrganization
Seen on GitHub Trending
- 2026-10-23 — #6 daily in systemverilog
- 2026-10-23 — #4 monthly in systemverilog · +66 ★
- 2026-10-23 — #2 weekly in systemverilog · +17 ★
- 2026-10-22 — #4 monthly in systemverilog · +68 ★
- 2026-10-22 — #1 weekly in systemverilog · +21 ★
- 2026-10-21 — #5 daily in systemverilog · +2 ★
- 2026-10-21 — #4 monthly in systemverilog · +67 ★
- 2026-10-21 — #1 weekly in systemverilog · +20 ★
- 2026-10-20 — #5 daily in systemverilog · +2 ★
- 2026-10-20 — #4 monthly in systemverilog · +65 ★
- 2026-10-20 — #1 weekly in systemverilog · +21 ★
GitHub topics
Links
- GitHub: github.com/lowRISC/ibex
- Homepage: https://www.lowrisc.org
- Releases · Issues · Hacker News mentions
README
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Blurb generated by claude-haiku-5-5 today. Star deltas marked ~ are extrapolated from partial history.