ESP-SDR uses the undocumented raw I/Q capture functionality of ESP32 family chips to turn them into (low-duty-cycle) Software Defined Radios
Radix Embodied Stack: Universal infrastructure for VLA model quantization, inference, and deployment on domestic chips . Cross-model, cross-chip, cross-platform.
🦾 A list of reported app support for Apple Silicon as well as Apple M4 and M3 Ultra Macs
The C-based Firmware Patching Framework for Broadcom/Cypress WiFi Chips that enables Monitor Mode, Frame Injection and much more
A Python library for designing chips (Photonics, Analog, Quantum, MEMS), PCBs, and 3D-printable objects. We aim to make hardware design accessible, intuitive, and fun—empowering everyone to build the future.
Javascript implementation of flasher tool for Espressif chips, running in web browser using WebSerial.
Chisel: A Modern Hardware Design Language
Platform Security Assessment Framework
Shredos Disk Eraser 64 bit for all Intel 64 bit processors as well as processors from AMD and other vendors which make compatible 64 bit chips. ShredOS - Secure disk erasure/wipe
This repo includes .NET Core implementations for various IoT boards, chips, displays and PCBs.
Open source firmware (Tasmota/Esphome replacement) for BK7231T, BK7231N, BL2028N, T34, XR809, W800/W801, W600/W601, BL602, LN882H, Realtek chips and more
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door is wide open for backdoor scrutiny, be it related to RTL, embedded, build, bitstream or any other aspect of design and delivery package. Bujrum!
Random instruction generator for RISC-V processor verification
8-bit chip and system emulators in standalone C headers
Generator Bootcamp Material: Learn Chisel the Right Way
A flutter package for creating badges.
面向 GPT-image-2 的 AI 图片生成 WebUI 工作台,支持 Codex Responses 与 OpenAI 兼容 API 接入,内置公用图库、多类型 Chip 快捷引用、提示词模板、多任务并发和本地队列管理。An AI image generation WebUI workbench for GPT-image-2 with Codex Responses and OpenAI-compatible API support, shared gallery references, multi-type quick chips, prompt templates, concurrent tasks, and local queue management.
TensorFlow Lite Micro for Espressif Chipsets
IMSProg - software for CH341A-based programmers to work with I2C, SPI and MicroWire EEPROM/Flash chips
Linux Kernel for Motorola devices using MSM-based chipset
Powering AWS purpose-built machine learning chips. Blazing fast and cost effective, natively integrated into PyTorch and TensorFlow and integrated with your favorite AWS services
EDA-Q is a full-stack electronic design automation (EDA) tool for quantum chip design, supporting both superconducting and trapped-ion quantum computing architectures. The platform enables researchers and engineers to efficiently design, simulate, and optimize quantum chips.
Tests and sample code for https://github.com/floooh/chips
BouffaloSDK is the IOT and MCU software development kit provided by the Bouffalo Lab Team, supports all the series of Bouffalo chips. Also it is the combination of bl_mcu_sdk and bl_iot_sdk
HW Design Collateral for Caliptra RoT IP
谛听 DITING:LLM 驱动的自主渗透测试工作台,Go + Next.js + PostgreSQL,基于 ARTEX(AGPL-3.0)
台灣市場籌碼資料的 Python 小工具:期交所日行情與三大法人、證交所三大法人與融資融券
A game framework for small chips like ESP32
HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.
Bluetooth in your Proxmox Linux VMs, finally. Pair controllers inside ChimeraOS/Bazzite/any Linux guest, even with Intel chips that can't be passed through.
A Big Box Amiga for MiSTer: the Minimig chipset in the FPGA, driven by the Emu68-A9 ARMv7 JIT running bare-metal on the second HPS core
Voodoo-1 3D graphics chipset in SystemVerilog
A local LLM server built for Qualcomm chips