ChengminLi / AI-PCB-layout

# AI PCB Layout
A gift for hardware engineer. 
An AI agent skill for **designing, reviewing, and improving power-electronics PCBs**. This skill does not produce a PCB at the first try, instead it provides a way of how to collobrate with the AI agents to boost the productivity of PCB layout. I expect that the user has at least midlevel hardware experience, thus can provide engineering judgement to review the results. 
The skill teaches an AI coding agent (Cursor, Claude Code, Codex, or any agent that supports `SKILL.md` skills) to work like a careful power-electronics layout engineer: it traces commutation and gate loops from the switching states, derives clearance and copper limits from standards and design currents, and **stops for your approval after every step**, so you stay in control of every design decision.
> **Note:** The skill helps you reach a well-reasoned design and tells you which evidence is still missing. It does not certify safety or EMC compliance. Measurements and the applicable standards remain the final authority.
## What it covers
- **Electrical net table:** worst-case peak voltage, dv/dt, RMS current, and di/dt for each key node and current path, taken from simulation or calculation, and turned into layout constraints
- **Switching loops:** commutation cells, gate charge and discharge loops, Kelvin connections, and common-mode paths, derived per switching transition
- **Insulation:** clearance, creepage, and solid insulation derived from the applicable standard and its inputs, never copied from example values
- **Copper capability:** conductor and via sizing from worst-case RMS current and permitted temperature rise
- **Placement and routing:** functional block floorplans, routability checks, and a routing plan you approve before any copper is drawn
- **Verification:** DRC, insulation geometry, parasitic extraction, re-simulation, and thermal checks, each recorded with its evidence type (CAD check, estimate, simulation, or measurement)
- **Delivery:** fabrication and assembly outputs, and a BOM with verified datasheet and order links
It works with any topology, device technology (Si, IGBT, SiC, GaN), and CAD tool. KiCad 9 is covered in the most detail; concept mappings are included for Altium Designer, Allegro/OrCAD, Xpedition/PADS, and Fusion.
## How it works
The agent works in nine steps. After each step it delivers a short report and waits for you to reply **approve**, **approve with changes**, **redo**, or **stop**.
 [code] 
You don't always need all nine steps. In step 1 you agree on a scope:
| Scope | What happens |
|---|---|
| **Review** an existing design | Reads your files and reports prioritized findings. No files are changed. |
| **Small revision** (label, footprint swap, local reroute) | Proposes the change for approval, then edits and rechecks only what it affects. |
| **Create or revise a layout** for an approved circuit | Footprints, rules, placement, routing, verification, and delivery. |
| **End-to-end desig