Scripts and Makefile flow that run RTL-to-GDSII physical design end to end using the OpenROAD toolchain.
Starter template for building Verilog designs that get fabricated on a Tiny Tapeout SKY130 shuttle chip.
Scripts and Makefile flow that run RTL-to-GDSII physical design end to end using the OpenROAD toolchain.
Starter template for building Verilog designs that get fabricated on a Tiny Tapeout SKY130 shuttle chip.