jonathansong / Torch2RISCV-accelerator

An end-to-end compiler stack that lowers PyTorch models to a custom RISC-V instruction set, running on a heterogeneous **ARM (host) + PicoRV32 (control core) + systolic-array accelerator** built on a PYNQ-Z1 board.

YutongChenVictor / NPU-E2E

End-to-End NPU: RTL systolic array → AXI4 SoC → TVM compiler → FPGA inference