pulp-platform / axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
pulp-platform / axi
a2307588073-arch / zynq-yolov3-tiny-accelerator
INT8 single-class YOLOv3-Tiny accelerator and OV5640-to-HDMI bare-metal demo for Xilinx Zynq-7000 XC7Z100, with PyTorch training and parameter-export tools. Topics yolov3-tiny, fpga, zynq-7000, xc7z100, verilog, vivado, vitis, pytorch, int8-quantization, object-detection, axi4-stream, ov5640, hdmi, embedded-systems, computer-vision
YutongChenVictor / NPU-E2E
End-to-End NPU: RTL systolic array → AXI4 SoC → TVM compiler → FPGA inference