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open-sdr / openwifi

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

▲ ~12/7d ★ 4.9k C 1d ago
open-sdr / openwifi-hw

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

▲ ~5/7d ★ 914 Verilog 10d ago
Xilinx / PYNQ

Python Productivity for ZYNQ

▲ ~2/7d ★ 2.4k Jupyter Notebook 7d ago
a2307588073-arch / zynq-yolov3-tiny-accelerator

INT8 single-class YOLOv3-Tiny accelerator and OV5640-to-HDMI bare-metal demo for Xilinx Zynq-7000 XC7Z100, with PyTorch training and parameter-export tools. Topics yolov3-tiny, fpga, zynq-7000, xc7z100, verilog, vivado, vitis, pytorch, int8-quantization, object-detection, axi4-stream, ov5640, hdmi, embedded-systems, computer-vision