Implement yolov26m using a complete FPGA, without any C language code. Requires 160K LUTs and 386 DSP cores (based on Xilinx XC7K325T).
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open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
Python Productivity for ZYNQ
Universal utility for programming FPGA
Brevitas: neural network quantization in PyTorch
The official Linux kernel from Xilinx
Dataflow compiler for QNN inference on FPGAs
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware
OpenOnload high performance user-level network stack
A close-to-metal Python API for programming AMD Ryzenβ’ AI NPUs (AI Engines), built on an open-source MLIR-based compiler toolchain.
Run Time for AIE and FPGA based platforms
The official Xilinx u-boot repository
INT8 single-class YOLOv3-Tiny accelerator and OV5640-to-HDMI bare-metal demo for Xilinx Zynq-7000 XC7Z100, with PyTorch training and parameter-export tools. Topics yolov3-tiny, fpga, zynq-7000, xc7z100, verilog, vivado, vitis, pytorch, int8-quantization, object-detection, axi4-stream, ov5640, hdmi, embedded-systems, computer-vision