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fromgof / TridentVision

Implement yolov26m using a complete FPGA, without any C language code. Requires 160K LUTs and 386 DSP cores (based on Xilinx XC7K325T).

β–² ~14/7d β˜… 296 Verilog 1mo ago
open-sdr / openwifi

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

β–² ~7/7d β˜… 4.8k C 5d ago
Xilinx / PYNQ

Python Productivity for ZYNQ

β–² ~0/7d β˜… 2.4k Jupyter Notebook 6d ago
Xilinx / brevitas

Brevitas: neural network quantization in PyTorch

β–² ~0/7d β˜… 1.6k Python 3d ago
Xilinx / finn

Dataflow compiler for QNN inference on FPGAs

β–² ~0/7d β˜… 1.1k Python 1d ago
open-sdr / openwifi-hw

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

β–² ~0/7d β˜… 913 Verilog 9d ago
Xilinx-CNS / onload

OpenOnload high performance user-level network stack

β–² ~0/7d β˜… 851 C 5d ago
Xilinx / mlir-aie

A close-to-metal Python API for programming AMD Ryzenβ„’ AI NPUs (AI Engines), built on an open-source MLIR-based compiler toolchain.

β–² ~0/7d β˜… 706 C today
Xilinx / XRT

Run Time for AIE and FPGA based platforms

β–² ~0/7d β˜… 692 C++ 1d ago
a2307588073-arch / zynq-yolov3-tiny-accelerator

INT8 single-class YOLOv3-Tiny accelerator and OV5640-to-HDMI bare-metal demo for Xilinx Zynq-7000 XC7Z100, with PyTorch training and parameter-export tools. Topics yolov3-tiny, fpga, zynq-7000, xc7z100, verilog, vivado, vitis, pytorch, int8-quantization, object-detection, axi4-stream, ov5640, hdmi, embedded-systems, computer-vision