π¬ Vite plugin that provide checks of TypeScript, ESLint, vue-tsc, Stylelint and more.
An open-source static random access memory (SRAM) compiler.
Magic VLSI Layout Tool
SystemVerilog language server
A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
IP Subnet Calculator β Enter any IPv4 address with a CIDR prefix or subnet mask to instantly get the network address, broadcast address, usable host range, wildcard mask, binary/hex breakdown, and classification. Includes a VLSM planner, subnet list generator, and reverse calculators for required hosts or subnets. Free on ToolAdda.online.
RTL Generation AI Flow