openhwfoundation / cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

sysprog21 / shecc

A self-hosting and educational C optimizing compiler

sysprog21 / rv32emu

Compact and Efficient RISC-V RV32I[MAFC] emulator

adityarajIITj / adios

An ultra-lightweight, zero-bloat bare-metal operating system built from scratch for a custom RISC-V (RV32I) simulation layer. Featuring preemptive multitasking, page frame allocation, a custom toolchain, and an interactive shell.

cwu766485-ctrl / LumenRV32

A lightweight RV32I RISC-V processor core implemented in Verilog for architecture and RTL design practice.