pulp-platform / axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

pulp / pulpcore

Pulp 3 pulpcore package https://pypi.org/project/pulpcore/

coin-or / pulp

A python Linear Programming API

openhwfoundation / cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

pulp-platform / ara

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

pulpul-s / HWall

Linux hardware inventory and live sensor monitor

ARA-Labs / PULP-LLM

Teach an Open Model Everything About Your Chip