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VLSIDA / OpenRAM

An open-source static random access memory (SRAM) compiler.

▲ ~0/7d ★ 1.2k Python 1d ago
emsec / hal

HAL – The Hardware Analyzer

▲ ~0/7d ★ 838 C++ 1d ago
StefanSchippers / xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

▲ ~0/7d ★ 502 C today
Tencent / wave-mcp

Open-source, license-free MCP server for RTL waveform debug: reads FST waveforms (VCD/FSDB auto-convert) plus a SystemVerilog netlist, with 34 tools covering driver analysis, value/X tracing, pass-fail waveform diff, a browser wave viewer the agent drives, and pre-simulation static analysis.