Haskell to VHDL/Verilog/SystemVerilog compiler
PypelineC: A hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
Haskell to VHDL/Verilog/SystemVerilog compiler
PypelineC: A hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.