OpenXiangShan / XiangShan

Open-source high-performance RISC-V processor

ucb-bar / gemmini

Berkeley's Spatial Array Generator

ucb-bar / chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

chipsalliance / chisel

Chisel: A Modern Hardware Design Language

THU-DSP-LAB / ventus-gpgpu

GPGPU processor supporting RISCV-V extension, developed with Chisel HDL

chipsalliance / rocket-chip

Rocket Chip Generator

riscv-boom / riscv-boom

SonicBOOM: The Berkeley Out-of-Order Machine

YeXiHuTeam / YeXiHuCore

USTC YeXiHu Team NSCSCC 2026 LA32R out-of-order processor core in Chisel. 中国科学技术大学也西湖队龙芯杯参赛项目。