Abdess / retrobios

Source-verified BIOS and firmware packs for RetroArch, Batocera, Recalbox, Lakka, RetroPie, EmuDeck, RetroBat, RetroDECK, RomM, BizHawk, ROCKNIX, and MiSTer FPGA. Platform-native verification, with emulator source code as the deciding authority.

enjoy-digital / litex

Build your hardware, easily!

GlasgowEmbedded / glasgow

Scots Army Knife for electronics

fastmachinelearning / hls4ml

Machine learning on FPGAs using HLS

Xilinx / brevitas

Brevitas: neural network quantization in PyTorch

olofk / fusesoc

Package manager and build abstraction tool for FPGA/ASIC development

siliconcompiler / siliconcompiler

Modular hardware build system

YosysHQ / icestorm

Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)

Woolverine94 / biniou

a self-hosted webui for 30+ generative ai

Xilinx / finn

Dataflow compiler for QNN inference on FPGAs

FPGAwars / apio

:seedling: Open source ecosystem for open FPGA boards

JulianKemmerer / PipelineC

PypelineC: A hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

YosysHQ / apicula

Project Apicula 🐝: bitstream documentation for Gowin FPGAs

spcl / dace

DaCe - Data Centric Parallel Programming

SigmanticAI / apex-inference-chip

An inference chip design that runs a real LLM (Qwen2.5-0.5B) on FPGA — one transformer decoder layer in RTL, every silicon value bit-exact against a golden model. 0.56 tok/s measured, a 140× climb, full evidence trail.