RISC-V SoC designed by students in UCAS
USTC YeXiHu Team NSCSCC 2026 LA32R out-of-order processor core in Chisel. 中国科学技术大学也西湖队龙芯杯参赛项目。
RISC-V SoC designed by students in UCAS
USTC YeXiHu Team NSCSCC 2026 LA32R out-of-order processor core in Chisel. 中国科学技术大学也西湖队龙芯杯参赛项目。