A secure embedded operating system for microcontrollers
A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host
SP1 is a zero‑knowledge virtual machine that proves the correct execution of programs compiled for the RISC-V architecture.
RISC-V Supervisor Binary Interface (RISC-V SBI) library in Rust; runs on M or HS mode; good support for embedded Rust ecosystem. For binary download see firmware folder.
Unix-like OS in Rust inspired by xv6-riscv
Low level access to RISC-V processors
A Rust-based x86-64 PE protection framework with RISC program virtualization, polymorphic VM bytecode, CFG transformation, runtime hardening, integrity checks, and execution verification.