Radix Embodied Stack: Universal infrastructure for VLA model quantization, inference, and deployment on domestic chips . Cross-model, cross-chip, cross-platform.
仕事の日本語を、読みやすくわかりやすく書く・直すための Agent Skill です。
Build your hardware, easily!
cocotb: Python-based chip (RTL) verification
A Python library for designing chips (Photonics, Analog, Quantum, MEMS), PCBs, and 3D-printable objects. We aim to make hardware design accessible, intuitive, and fun—empowering everyone to build the future.
ASIC implementation flow infrastructure, successor to OpenLane
Self-hosted AI agent OS. Your memory, chat, agents, and files stay on hardware you own, offline by default, cloud by choice. Offline AI memory (taOSmd), self-hosted multi-framework group chat, a full web desktop + app store, and auto-clustering across the consumer hardware you already have (Orange/Raspberry Pi, Mac mini, gaming PC).
Per-provider quota and rate limits in Hermes Desktop: a status-bar chip, a docked pane, the /quota command and a CLI — fed from a local cache, with no network I/O in the UI.
Reverse-engineering a JieLi AC707N/BR35 BLE e-badge (E87): BLE clients, pure-Python UFW tooling, chipkey/flash helpers, SDK build scripts, and self-built firmware. Security research / educational.
Platform Security Assessment Framework
Archipelago Multi-Game Randomizer and Server
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Random instruction generator for RISC-V processor verification
CatSniffer is an original multiprotocol and multiband board for sniffing, communicating, and attacking IoT (Internet of Things) devices using the latest radio IoT protocols. It is a highly portable USB stick that integrates TI CC1352, Semtech SX1262, and an RP2040 for V3 or a Microchip SAMD21E17 for V2
MACS -- Model-based Analysis of ChIP-Seq
Tools to process and analyze deep sequencing data.
Python Filter Design Analysis Tool
Powering AWS purpose-built machine learning chips. Blazing fast and cost effective, natively integrated into PyTorch and TensorFlow and integrated with your favorite AWS services
An inference chip design that runs a real LLM (Qwen2.5-0.5B) on FPGA — one transformer decoder layer in RTL, every silicon value bit-exact against a golden model. 0.56 tok/s measured, a 140× climb, full evidence trail.
Open-source, license-free MCP server for RTL waveform debug: reads FST waveforms (VCD/FSDB auto-convert) plus a SystemVerilog netlist, with 34 tools covering driver analysis, value/X tracing, pass-fail waveform diff, a browser wave viewer the agent drives, and pre-simulation static analysis.
台灣市場籌碼資料的 Python 小工具:期交所日行情與三大法人、證交所三大法人與融資融券
Reverse-engineered docs and tools for 8BitDo firmware encryption methods